Zero Delay Buffer 14-Out CMOS/HSTL/LVDS/LVPECL Differential 72-Pin LFCSP EP T/R
PRODUCTION (Last Updated: 4 months ago)
8 Weeks
Tin
表面贴装
72-VFQFN Exposed Pad, CSP
YES
72
1GHz
-40°C~85°C
Tape & Reel (TR)
e3
no
活跃
3 (168 Hours)
72
EAR99
3.3V
QUAD
260
0.5mm
30
AD9523
HSTL, LVCMOS, LVDS, LVPECL
72
14
3.3V
1
75.8mA
CLOCK GENERATOR, OTHER
CMOS
2:14
400MHz
有
Yes/Yes
Ethernet, Fibre Channel, SONET/SDH
无
ROHS3 Compliant
含铅
-
-
-
-
-
Zero Delay PLL Clock Generator Dual 72-Pin LFCSP EP T/R
PRODUCTION (Last Updated: 1 month ago)
10 Weeks
Tin
表面贴装
72-VFQFN Exposed Pad, CSP
YES
72
1GHz
-40°C~85°C
Tape & Reel (TR)
e3
no
活跃
2 (1 Year)
72
EAR99
1.8V
QUAD
260
0.5mm
30
AD9523
HSTL, LVCMOS, LVDS, LVPECL
72
14
3.3V
1
77.7mA
-
CMOS
2:14
-
有
Yes/Yes
Ethernet, Fibre Channel, SONET/SDH
-
ROHS3 Compliant
含铅
无铅
1
952
基于PLL的时钟驱动器
0.3 ns