Teledyne e2v 5962-9056402XA

HTS

8542.31.00.01

Instruction Set Architecture

CISC

Maximum CPU Frequency (MHz)

33

Maximum Clock Rate (MHz)

33

Data Bus Width (bit)

8

Programmability

无

USART

0

UART

0

I2C

0

I2S

0

CECC Qualified

无

Standard Package Name

DIP

Supplier Package

PDIP

Mounting

通孔

Package Height

4(Max)

Package Length

52.5(Max)

Package Width

14.1(Max)

PCB changed

40

Lead Shape

通孔

零件状态

活跃

引脚数量

40

内存大小

512B

程序存储器类型

ROMLess

核心架构

8051

以太网

0

USB

0

SPI,SPI

0

CAN

0

设备核心

8051

RoHS状态

RoHS non-compliant