ALTERA EP910IDI-25

表面安装

NO

终端数量

40

Package Description

WDIP,

Package Style

IN-LINE, WINDOW

Package Body Material

CERAMIC, GLASS-SEALED

Operating Temperature-Min

-40 °C

Supply Voltage-Nom

5 V

Supply Voltage-Min

4.5 V

Operating Temperature-Max

85 °C

Manufacturer Part Number

EP910IDI-25

Clock Frequency-Max

40 MHz

Package Code

WDIP

Package Shape

RECTANGULAR

Manufacturer

Altera Corporation

Part Life Cycle Code

Obsolete

Number of I/O Lines

24

Ihs Manufacturer

ALTERA CORP

Supply Voltage-Max

5.5 V

Risk Rank

5.52

Part Package Code

DIP

ECCN 代码

EAR99

附加功能

MACROCELLS INTERCONNECTED BY GLOBAL BUS; 24 MACROCELLS; 2 EXTERNAL CLOCKS

HTS代码

8542.39.00.01

技术

CMOS

端子位置

DUAL

终端形式

THROUGH-HOLE

端子间距

2.54 mm

Reach合规守则

unknown

引脚数量

40

JESD-30代码

R-GDIP-T40

资历状况

不合格

温度等级

INDUSTRIAL

传播延迟

28 ns

组织结构

12 DEDICATED INPUTS, 24 I/O

座位高度-最大

5.75 mm

可编程逻辑类型

UV PLD

输出功能

MACROCELL

专用输入数量

12

宽度

15.24 mm

长度

52.07 mm