EDAC 346-100-558-301

Maximum Clock Rate

250 MHz

Supplier Package

FBGA

Data Rate Architecture

DDR

Typical Operating Supply Voltage

1.8000 V

Minimum Operating Supply Voltage

1.7 V

Timing Type

Synchronous

Number of Words

512 kWords

Number of I/O Lines

36 Bit

Maximum Operating Supply Voltage

1.9 V

Mounting

表面贴装

Usage Level

Commercial grade

操作温度

0 to 70 °C

引脚数量

165

端口的数量

1

建筑学

Pipelined

地址总线宽度

19 Bit

密度

18 Mb

筛选水平

Commercial